1. Field
The embodiment relates to a method of designing and producing semiconductor integrated circuits, and particularly to a method and a program designing semiconductor integrated circuits.
2. Description of the Related Art
Static timing analysis (STA) is conventionally employed as a method of verifying timing in semiconductor integrated circuits (such as an LSI circuit). In STA, timing in circuits is verified on the basis of delay times that are respectively assigned to cells that constitute a semiconductor integrated circuit.
Factors that affect variations in signal propagation delay in LSIs include (1) variations in process properties such as transistor properties of transistors that constitute LSIs, (2) variations in power supply voltage caused by a voltage drop inside the chip, and (3) variations in temperature inside the chip. These variations are called on-chip variations (OCV). It is very difficult to strictly take each OCV into consideration, and in conventional STA, variations of property values (such as delay time, for example) are expressed by uniform variation coefficients for respective cells that constitute LSIs in order to verify whether or not the semiconductor integrated circuit can operate normally. As the uniform variation coefficients, relatively large values are used to cover all the cases.
However, as processes have been miniaturized in recent years, variations in dimensions such as the gate width of transistors that constitute a cell become greater, and the timing margins on designs become greater when uniform variation coefficients are used for each cell, which is problematic in view of design.
FIGS. 1 and 2 show the conventional problem. FIG. 1 shows an example of a design of a transistor. In FIG. 1, the length of the gate is L, and the width of the gate is W that faces the active areas Many properties of transistors are determined by this gate width W.
FIG. 2 shows the relationship between the gate width W and the on-state current that is one of the transistor properties. When the gate width W becomes small, the range of the variation coefficient (ratio to the target value) expressing the variations of the property value (the interval between the upper and lower limits) becomes wider and when the variation coefficient for the small gate width is used uniformly, the timing margins on designs of the large gate width becomes too great, which is problematic.
Patent Document 1 discloses, as a conventional technique of timing analysis, a method of calculating a delay time; with this method timings can be efficiently verified by calculating a correction value for the variation coefficients on the basis of the function by which the propagation delay time can be approximated as the propagation delay time caused by variations in an actual chip in accordance with the number of cell stages in a signal path, and by calculating the propagation delay time while taking into consideration the corrected variation coefficients.
Patent Document 2 discloses, as another conventional technique, a timing analysis device that can perform accurate timing analysis by calculating the OCV coefficient that has been obtained by taking into consideration the number of cell stages on the basis of the idea that an increased number of cell stages reduces the range of variations of, for example, the delay time because the variations in the cell property are in accordance with the normal distribution.
However, even when these conventional techniques are used, there remains a problem that cannot be solved: the design has further difficulties due to variations in the transistor's dimensions (such as gate width) that will likely become greater as processes are miniaturized.    Patent Document 1    Republication of Patent No. WO2003/060776 “METHOD AND SYSTEM FOR CALCULATING DELAY TIME IN SEMICONDUCTOR INTEGRATED CIRCUIT”    Patent Document 2    Japanese Patent Application Publication No. 2005-122298 “DEVICE, METHOD, AND PROGRAM FOR ANALYZING TIMING”